1. Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to a NAND type multi-bit charge storage memory array and methods for operating and fabricating the same.
2. Description of the Related Art
Demand for flash memories is growing rapidly due to the wide range of portable and embedded products with increased storage requirements. NAND type flash memory is one type of memory structure that is commonly used, however, conventional NAND type flash memory arrays will require many select transistors. This is especially true for multi-bit per cell applications.
A conventional NAND floating gate memory array 100 is depicted in FIG. 1. The NAND floating gate memory array 100 includes four memory strings each of which connects one string select transistor, one ground select transistor, and six floating gate memory cells in series. Each of the four memory strings has one end connected to a bit line and the other end connected to a common source line. The drain regions of the string select transistors SST1, SST2, SST3, and SST4 are respectively connected to the bit lines BL1, BL2, BL3, and BL4 through contacts. The source regions of the ground select transistors GST1, GST2, GST3, and GST4 are connected to the common source line.
As shown in FIG. 1, the string select transistors SST1, SST2, SST3, and SST4 are controlled by the String Select line (SSL), whereas the ground select transistors GST1, GST2, GST3, and GST4 are controlled by the Ground Select line (GSL). The twenty-four floating gate memory cells of the four memory strings are arranged in 4 columns and six rows. Each floating gate memory row is driven by a word line (WL). For example, the floating gate memory cells M11, M21, M31, and M41 of the first row are driven by the word line WL1.
Since the conventional NAND floating gate memory array 100 uses floating gate memory cells to store data, it is only capable of one bit per cell operation. In addition, the layout of the conventional NAND floating gate memory array 100 requires double polysilicon layers and double metal layers, which complicates the fabrication process. Furthermore, due to the small contact pitch between bit lines, the bit line contact process of the conventional NAND floating gate memory array 100 needs to be very precise.
In view of the foregoing, there is a need for a new NAND memory array and methods for operating and fabricating such a NAND memory array so that the NAND memory array is capable of multiple bits per cell operation and requires simple fabrication process.